AMD introduces Spartan UltraScale+ programmable logic chips for edge applications

AMD introduced its Spartan UltraScale+ programmable logic chips for edge applications.

The Santa Clara, California-based company said its latest field programmable gate arrays — FPGAs, a chip family acquired with its $49 billion purchase of Xilinx — are designed for cost-sensitive edge applications.

These advanced FPGAs bring high input/output (I/O) counts, power efficiency, and cutting-edge security features, catering to diverse industries such as embedded vision, healthcare, industrial networking, robotics, and video applications.

“This is our sixth generation Spartan FPGA product line. These are some of the most ubiquitous FPGAs in the industry, well known in the programmable logic space,” said Rob Bauer, senior manager of product marketing at AMD, in a press briefing. “It’s important to remember that Spartan is really empowering our world from the everyday technology all the way through to some of these breakthrough advances.”

The Spartan UltraScale+ devices represent a significant leap forward in FPGA technology, offering the industry’s highest I/O to logic cell ratio in FPGAs built on 28-nanometer (nm) chip manufacturing nodes. It has up to 30% lower total power consumption compared to the previous generation and better performance.

“For over 25 years, the Spartan FPGA family has played a vital role in powering achievements ranging from Mars rovers to life-saving automated defibrillators,” said Kirk Saban, corporate vice president in the Adaptive and Embedded Computing Group at AMD, in a statement. “The Spartan UltraScale+ family builds on proven 16nm technology, modernizing features, common design tools, and long product lifecycles to strengthen our market-leading FPGA portfolio and demonstrate our commitment to maximizing design longevity for customers.”

Flexible I/O and power efficiency

The Spartan UltraScale+ FPGAs are tailored for edge computing, offering high I/O counts and flexible interfaces that seamlessly integrate and interface with multiple devices or systems. With up to 572 I/Os and voltage support up to 3.3V, these FPGAs enable versatile connectivity for edge sensing and control applications. The family’s 16-nm fabric and support for various packaging sizes provide high I/O density in a compact footprint.

Spartan UltraScale+ FPGAs are estimated to reduce power consumption by up to 30% compared to the 28nm Artix 7 family. Leveraging 16nm FinFET technology and hardened connectivity, these FPGAs are equipped with a hardened LPDDR5 memory controller and PCIe Gen4 x8 support, ensuring both power efficiency and future-ready capabilities for users.

Security is a paramount concern in edge applications, and the Spartan UltraScale+ FPGAs address this by offering security features like Post-Quantum Cryptography with NIST-approved algorithms, ensuring IP protection against evolving cyber threats. A physical unclonable function provides each device with a unique fingerprint for enhanced security.

“Security is another aspect we want to touch on as we have more devices at the edge collecting more data,” Bauer said. “So the privacy of the user and protection of intellectual property is increasingly important. As we get more devices at the edge, the need for security is becoming a table stake for our customers.”

To prevent tampering, PPK/SPK key support helps manage obsolete or compromised security keys, while differential power analysis safeguards against side-channel attacks. The devices also incorporate a permanent tamper penalty to further protect against misuse. Enhanced single-event upset performance ensures fast and secure configuration with increased reliability.

The entire AMD FPGA portfolio, including the Spartan UltraScale+ family, is supported by the AMD Vivado Design Suite and Vitis Unified Software Platform. This allows hardware and software designers to leverage the productivity benefits of these tools and included IPs through a single designer cockpit from design to verification.

The AMD Spartan UltraScale+ FPGA family is slated for sampling and evaluation kits in the first half of 2025, with documentation available immediately. Tools support is expected to commence with the AMD Vivado Design Suite in the fourth quarter of 2024. The Spartan chips were first introduced in 1998.